CIRCUIT AND METHOD FOR ERASING EEPROM MEMORY ARRAYS

The device and process of this invention provide for eliminating reading errors caused by over-erased cells (10) by applying flash erasing pulses (Vee), then flash programming pulses (Vpp) to the cells of an EEPROM array. The flash erasing pulses (Vee) are sufficient in strength to over-erase the ce...

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Bibliographic Details
Main Author SANTIN, GIOVANI
Format Patent
LanguageEnglish
Published 23.12.1992
Edition5
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:The device and process of this invention provide for eliminating reading errors caused by over-erased cells (10) by applying flash erasing pulses (Vee), then flash programming pulses (Vpp) to the cells of an EEPROM array. The flash erasing pulses (Vee) are sufficient in strength to over-erase the cells (10). The flash programming pulses (Vpp) applied to the control gates (14) have the same voltages as those used to program individual cells (10). The strength of the programming electric field pulses adjacent the floating gates (13) is controlled by applying a biasing voltage (Vbb) to one of the source/drain regions (11/12) of the cells. The biasing voltage (Vbb) controls the energy level of the programming field pulses such that only enough charge is transferred to the floating gates (13) to cause the threshold voltages of the cells (10) to have positive values less than that of a predetermined wordline select voltage (Vcc).
Bibliography:Application Number: EP19910104997