Wafer scale memory having improved multi-bit accessing and system having the wafer scale memory

• Main Author: IKEHARA, SHOHEI
• Format: Patent
• Language: English; French; German
• Published: 11.09.1991
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A wafer scale memory includes a wafer (13), a plurality of memory chips (10) arranged into rows and columns, address lines provided for the respective columns, N data lines (16) provided for the respective columns where N is an arbitrary integer, and common signal lines (15) provided for the respective columns. Each of the memory chips includes a data storage circuit (26) having a plurality of memory cells, data being written into or read out from the data storage circuit via a corresponding one of the N data lines, and the memory cells being specified by an in-chip address signal transferred via a corresponding one of the common signal lines. Each of the memory chips also includes a register (22) for registering a chip address of a corresponding one of the memory chips in which the above register is provided, and a comparing part (24, 34) for comparing the chip address stored in the register with a chip address transferred via a corresponding one of the address lines and for generating an instruction signal showing that the corresponding one of the memory chips is selected when the chip address stored in the register is the same as the chip address transferred via the corresponding one of the address lines.