Biasing circuit

A biasing circuit for use with memory cells in intermittent memories includes means coupled between first and second bit-lines for biasing continuously the first and second bit-lines during a read operation so as to compensate for any leakage of charge without consuming any power. The biasing means...

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Bibliographic Details
Main Author AUVINEN, STUART T
Format Patent
LanguageEnglish
French
German
Published 23.01.1991
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A biasing circuit for use with memory cells in intermittent memories includes means coupled between first and second bit-lines for biasing continuously the first and second bit-lines during a read operation so as to compensate for any leakage of charge without consuming any power. The biasing means is formed of an N-channel MOS biasing transistor (M1) and a cross-coupled half-latch circuit formed of a first P-channel MOS transistor (M2) and a second P-channel MOS transistor (M3).
Bibliography:Application Number: EP19900306059