High density dynamic ram cell

• Main Authors: YASHIRO, MASAAKI, TENG, CLARENCE WAN-HSING, MORINAGA, SHIGEKI
• Format: Patent
• Language: English; French; German
• Published: 12.12.1990
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area. A self-aligned process is used to form the source (14) and drain (12) for the pass gate transistor and automatic connection between the source of the transistor and the buried doping layer is made by the buried N+ layer. A sidewall silicon nitride passivation filament (38) is formed to protect the sidewalls of the interlevel insulator region between the first (30) and second (3-3, 3-4) polycrystalline silicon layers.