Semiconductor memory device having information indicative of presence of defective memory cells
A semiconductor memory device storing data having a unit of N bits (1) (N is an integer) includes M memory elements (M is an integer and larger than N) each divided into a plurality of blocks each having a plurality of memory cells each storing one-bit data, and M internal bus lines each carrying on...
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Main Author | |
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Format | Patent |
Language | English French German |
Published |
26.09.1990
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Subjects | |
Online Access | Get full text |
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Summary: | A semiconductor memory device storing data having a unit of N bits (1) (N is an integer) includes M memory elements (M is an integer and larger than N) each divided into a plurality of blocks each having a plurality of memory cells each storing one-bit data, and M internal bus lines each carrying one-bit data and connected to a corresponding one of the M memory elements. A designating circuit (3) receives an address signal from an external device and designates one of the plurality of blocks of each of the M memory elements so that M blocks are designated by the address signal. A ROM (6; 24a) stores information on whether or not each of the plurality of blocks of each of the M memory elements has a defective memory cell and outputs the information in accordance with the address signal. N external bus lines (4) individually carry one-bit data. A bus line switching circuit (5, 6) determines whether each of the M blocks designated by the designating circuit has a defective memory cell by referring to the information from the ROM, and selectively connects N internal bus lines among the M internal bus lines to the N external bus lines so that one of the M blocks which has a defective memory cell is prevented from being selected and another one of the M blocks is selected. |
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Bibliography: | Application Number: EP19900302882 |