Method of manufacturing a semiconductor integrated circuit having an interconnection wire embedded in a protective layer covering the semiconductor integrated circuit

• Main Authors: MOTOYAMA, TAKUSHI, SATO, YASUHISA
• Format: Patent
• Language: English; French; German
• Published: 22.07.1998
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method of manufacturing a semiconductor integrated circuit with a semiconductor body (10) defined by a top surface and formed therein at least one semiconductor device, a first layer (11) covering the top surface of the semiconductor body (10) and having at least one contact hole for exposing the top surface of the semiconductor body, a silicon nitride layer (50) enabling selective refractory metal growth in vapour phase and covering a top surface of an insulator layer (16), and a second insulator layer (51) covering a top surface of the silicon nitride layer (50). The method comprises the steps of forming a groove (52) in the second insulator layer (51) and the silicon nitride layer (50) such that the silicon nitride layer (50) is exposed from a side wall of the groove (52) at a bottom part of the groove and such that the groove exposes a top surface of the insulator layer (16) at the bottom part of the groove, the groove being formed such that the groove passes at least one of the contact holes, and depositing a refractory metal (53') on this the insulator layer (16) exposed at the bottom of the groove such that the refractory metal fills the groove.