CMOS LATCH CIRCUIT

• Main Authors: SANWO, IKUO JIMMY, SUTHAR, MUKESH BHOGILAL
• Format: Patent
• Language: English
• Published: 26.09.1990
• Edition: 5
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

A no-leak CMOS latch circuit (10) has a data input line (12) for supplying a low or high data signal, a single clock input line (14), a data storage node (16), a complementary data output node (18), and first and second power supply terminals. The latch (10) has an NMOS input transistor (24) for supplying either a low or degraded high data signal to the data storage node (16). A CMOS inverter (26) connects the data storage node (16) to the complementary data output node (18). A dynamic inverter (32) including three series-connected transistors (34,36,38) responds to the signals on the clock input line (14) and output node (18) to connect either the first or second power supply terminals to the data storage node (18). In this manner the data storage node (16) is maintained at a level that prevents static power dissipation from the CMOS inverter (26).