High performance memory imaging network for a real time process control system

A data communications arrangement for a distributed processor control system having a number of stations (12, 32) which can send and receive control data, includes a communications processor at each station effective for controlling the flow of control data over a serial communications bus. The comm...

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Main Authors IHRMAN, ROBERT THORNTON, HOUSER, KIRK DOUGLAS, JONES, DONALD JAMES, POEPSEL, DONALD AWBERT, STAAB, CARL JOSEPH, BOEHMER, ROBERT WILLIAM
Format Patent
LanguageEnglish
French
German
Published 13.12.1989
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A data communications arrangement for a distributed processor control system having a number of stations (12, 32) which can send and receive control data, includes a communications processor at each station effective for controlling the flow of control data over a serial communications bus. The communications processor (66) is coupled to a dual ported memory device (68) along with a functional processor (70) which is effective for carrying out the actual operations of the process. The communications control processor is further effective for assembling frames of control data (Fig. 4) according to a predetermined arrangement which gives a timing preference to a first category of data over a second category of data. The assembled frame of control data will then include all of the first category of data and, with time remaining from a timing goal, will include a portion of the second category of data.
Bibliography:Application Number: EP19890305845