DEVICE FOR DERIVING A SAMPLING RATE

The device comprises a synchronizing-signal separator (20), a phase-locked loop (23), comprising a phase comparator (25), a voltage-controlled oscillator (28) and a frequency divider (31). The device further comprises a gate circuit (26) having an input (S) coupled to the output of the synchronizing...

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Bibliographic Details
Main Author ZWAANS, BERNARDUS ANTONIUS MARIA
Format Patent
LanguageEnglish
Published 05.05.1993
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
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Summary:The device comprises a synchronizing-signal separator (20), a phase-locked loop (23), comprising a phase comparator (25), a voltage-controlled oscillator (28) and a frequency divider (31). The device further comprises a gate circuit (26) having an input (S) coupled to the output of the synchronizing-signal separator (20), and an input (5) for receiving a head-change signal (a). The output (36) of the gate circuit (26) is coupled to a control-signal input (37) of the frequency divider (31). The gate circuit (26) is adapted to generate the control signal at a first instant (t1) of a head change and to sustain this control signal until a second instant (t2) of detection of the n-th (preferably the first) synchronizing signal after the head change. The frequency divider (31), which comprises a counter (40), is adapted to inhibit the output signal (d) in response to the control signal, to set the count to a specific value, and to enable the counter at the second instant in order to realize frequency-division.
Bibliography:Application Number: EP19890201270