EXCLUSIVE-OR GATE CIRCUIT
The present invention is an Exclusive-OR circuit which uses a minimum number of components and which is particularly adapted for use as a building block for a parity checking circuit. The circuit only uses CMOS gates to reduce the number of included transistors.
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
23.01.1991
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Subjects | |
Online Access | Get full text |
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Summary: | The present invention is an Exclusive-OR circuit which uses a minimum number of components and which is particularly adapted for use as a building block for a parity checking circuit. The circuit only uses CMOS gates to reduce the number of included transistors. |
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Bibliography: | Application Number: EP19880906669 |