Process for fabricating integrated-circuit devices utilizing multilevel resist structure

This invention is a method of fabricating an integrated-circuit device by utilizing a multilevel structure that includes a planerizing layer (e.g.22). Reactive ion etching of the planarizing layer of a multilevel resist structure utilized to make integrated-circuit devices is carried out employing a...

Full description

Saved in:
Bibliographic Details
Main Author KORNBLIT, AVINOAM
Format Patent
LanguageEnglish
French
German
Published 07.01.1988
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:This invention is a method of fabricating an integrated-circuit device by utilizing a multilevel structure that includes a planerizing layer (e.g.22). Reactive ion etching of the planarizing layer of a multilevel resist structure utilized to make integrated-circuit devices is carried out employing a plasma derived from carbon dioxide. The etching step is characterized by high throughput, good linewidth control, negligible radiation damage and low sensitivity to process parameter variations.
Bibliography:Application Number: EP19870305355