Method for manufacturing integrated electronic devices, in particular high voltage P-channel MOS transistors

This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant (25) on the surface of an epitaxial layer (2), without masking, and arsenic implant (28) in predetermined locations of the epitaxial layer surface by means of an appropriate mask (27)....

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Bibliographic Details
Main Authors GALBIATI, PAOLA, CONTIERO, CLAUDIO, ANDREINI, ANTONIO
Format Patent
LanguageEnglish
French
German
Published 12.08.1987
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant (25) on the surface of an epitaxial layer (2), without masking, and arsenic implant (28) in predetermined locations of the epitaxial layer surface by means of an appropriate mask (27). A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms (72,35-37), but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N⁺ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted
Bibliography:Application Number: EP19870100765