CONTACT VIAS IN SEMICONDUCTOR DEVICES

A glass reflow step to round off sharp edges of contact vias (42,44) is typically included in processes for making integrated-circuit devices. In the course of making such devices with closely spaced vias, it has been found that unacceptable overhangs occur on the sidewalls of the vias. Neither chan...

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Bibliographic Details
Main Authors LEVY, ROLAND ALBERT, NASSAU, KURT
Format Patent
LanguageEnglish
Published 18.05.1988
Edition4
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A glass reflow step to round off sharp edges of contact vias (42,44) is typically included in processes for making integrated-circuit devices. In the course of making such devices with closely spaced vias, it has been found that unacceptable overhangs occur on the sidewalls of the vias. Neither changes in the composition of the glass nor modifications in the processing parameters of reflow were effective to avoid the overhang phenomenon. In accordance with the invention, it has been discovered that the overhang problem can be consistently avoided if the ratio of glass thickness (t) to via-to-via spacing (s) is about 0.4 or less.
Bibliography:Application Number: EP19860308709