Universal protocol data receiver

@ A universal protocol data receiver 100 is disclosed which is capable of receiving data streams in character mode and block'mode, providing flow control and error detection and correction. The receiver is divided into two stages 10, 11, separated by a first-in, first-out buffer register 12. Th...

Full description

Saved in:
Bibliographic Details
Main Authors MARSHALL, WILLIAM TODD, FRASER, ALEXANDER GIBSON, RIDDLE, GUY GREGORY
Format Patent
LanguageEnglish
French
German
Published 24.09.1986
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Online AccessGet full text

Cover

More Information
Summary:@ A universal protocol data receiver 100 is disclosed which is capable of receiving data streams in character mode and block'mode, providing flow control and error detection and correction. The receiver is divided into two stages 10, 11, separated by a first-in, first-out buffer register 12. The first stage handles flow control and error processing as well as initialization. The second stage handles interfacing with the data utilizing mechanism and flow control acknowledgements. The FIFO buffer is divided into two parts by a movable barrier which limits the access of the second stage. The barrier permits error processing by hiding incoming blocks of data behind the barrier until processing is complete. Both a hardware and a software implementation of the receiver are disclosed.
Bibliography:Application Number: EP19860301807