SERIAL CHIP SCAN

Disclosed is a scan apparatus (4) which provides an interface and control signals between a secondary computer (1) and data locations in a host computer (2). The scan apparatus (4) functions independently of the normal operation of the host computer (2). Scan-out is performed transparently to the op...

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Bibliographic Details
Main Authors SHACKLEFORD, JAMES B, SI, STEPHEN S. C, ALLRED, DARYL H
Format Patent
LanguageEnglish
Published 16.09.1987
Edition4
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:Disclosed is a scan apparatus (4) which provides an interface and control signals between a secondary computer (1) and data locations in a host computer (2). The scan apparatus (4) functions independently of the normal operation of the host computer (2). Scan-out is performed transparently to the operation of the host computer (2). The host computer (2) is constructed using circuits on semiconductor chips (7-1. 7-Y). The semiconductor chips (7-1, 7-Y) are organized in blocks (3-1). Chips within each block (3-1) include scan apparatus (4) which controls the scan operations in connection with that chip. The scan apparatus in each chip is connected through two I/O pins to a clock lines and to a bidirectional scan data line. The scan apparatus on each chip includes a multimode sequencer so that each chip in each block can be independently performing scan sequences. The block scan apparatus and the secondary computer perform the functions of requesting a scan sequence for transmitting the scan data.
Bibliography:Application Number: EP19840305851