Timing system

A central clock signal generator generates a plurality of odd and even clock pulses which are distributed to a plurality of logic and circuit modules by clock signal lines of equal length. The central signal generator also generates a plurality of gate pulses which are supplied to the modules on sig...

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Bibliographic Details
Main Authors ROCHE, THOMAS JAMES, OZA, BHARAT JAYANTILAL
Format Patent
LanguageEnglish
French
German
Published 10.08.1983
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A central clock signal generator generates a plurality of odd and even clock pulses which are distributed to a plurality of logic and circuit modules by clock signal lines of equal length. The central signal generator also generates a plurality of gate pulses which are supplied to the modules on signal lines which can be different in length from one to another. The gate pulses are wide enough to coincide with the clock pulses with appropriate allowance for skew between the pulses. For each pair of pulses engaged delivered to a module a detection circuit is provided which detects if the gate pulse and the clock pulse begin and end in the proper sequence. If an improper sequence occurs, the information is stored in a scannable latch and a machine stop control is generated. The exact failing module can be traced readily from the information supplied in this manner.
Bibliography:Application Number: EP19820111110