SPEED-POWER SCALING FOR MOS CIRCUIT

The power consumption and corresponding speed of an integrated circuit is scaled by means of adjusting the channel width for MOS transistors. A transistor (12) is initially fabricated with a channel (24) having a width W1. The channel (24) receives a depletion type implant (30) to make the transisto...

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Bibliographic Details
Main Author SHEPPARD, DOUGLAS PARKS
Format Patent
LanguageEnglish
Published 17.04.1985
Edition4
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The power consumption and corresponding speed of an integrated circuit is scaled by means of adjusting the channel width for MOS transistors. A transistor (12) is initially fabricated with a channel (24) having a width W1. The channel (24) receives a depletion type implant (30) to make the transistor (12) lightly depleted. An enhancement implant (32) is applied to the channel (24) to cover a selected area (24a). The enhancement implant (32) is made substantially stronger than the depletion implant (30). This results in a first section (24a) of the channel (24) having a large threshold voltage while the second section (24b) of channel (24) has a relatively small pinch-off voltage. The size of the second section (24b) is selectively controlled to scale the source-drain current of transistor (12) and the corresponding power consumption of the transistor (12). The method of applying the first and second implants (30, 32) can be easily incorporated into conventional ROM fabrication without the need for additional manufacturing steps.
Bibliography:Application Number: EP19820111416