Redundanzschaltung für Halbleiterspeichergeräte

A row redundancy circuit repairs row defects generated in a given memory cell by the use of a redundant memory cell. In the row redundancy circuit, when the number of defective word lines generated in a first normal memory cell array 20L is greater than the number of redundant word lines available i...

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Bibliographic Details
Main Author LEE, KYUAN
Format Patent
LanguageGerman
Published 05.09.2002
Edition7
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A row redundancy circuit repairs row defects generated in a given memory cell by the use of a redundant memory cell. In the row redundancy circuit, when the number of defective word lines generated in a first normal memory cell array 20L is greater than the number of redundant word lines available in a first redundant memory cell array 30L, one fuse box 80L,80R controls each sense amplifier 40L,40R of adjacent memory arrays 20L,20R simultaneously, and a second redundant memory cell array 30R repairs a defective address of the first normal memory cell array 20L. Therefore, there is no need to increase the size or number of the fuse boxes 80L,80R and the redundancy efficiency may be greatly increased.
Bibliography:Application Number: DE19936030731T