Halbleiterspeichervorrichtung

A semiconductor memory cell comprises a first cascade gate, formed on a semiconductor substrate, having its end connected to a first node (N1), and a plurality of MOS transistors (Q1 to Q4) which are connected in cascade, a plurality of data storage capacitors (C1 to C4), formed on the semiconductor...

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Bibliographic Details
Main Authors TAKASE, SATORU, FURUYAMA, TOHRU
Format Patent
LanguageGerman
Published 01.10.1998
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:A semiconductor memory cell comprises a first cascade gate, formed on a semiconductor substrate, having its end connected to a first node (N1), and a plurality of MOS transistors (Q1 to Q4) which are connected in cascade, a plurality of data storage capacitors (C1 to C4), formed on the semiconductor substrate, each of which has its end connected to that end of a corresponding one of the MOS transistors which is opposite to the first node, and a device isolation MOS transistor (Q0) formed between the memory cell and another semiconductor memory cell which are arranged side by side on the semiconductor substrate.
Bibliography:Application Number: DE19926025298T