Adressaktivierungsanordnung und Verfahren für Speichermodule

A memory circuit for use in a data processing system which is acccessed by address signals and includes interconnection means for at least one memory module, which at least one memory module may or may not be present, and means for transmitting the address signals to the interconnection means if and...

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Bibliographic Details
Main Authors STEWART, GREG. N, HOLMAN, THOMAS H. JR, DURKIN, MICHAEL D
Format Patent
LanguageGerman
Published 17.08.2000
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory circuit for use in a data processing system which is acccessed by address signals and includes interconnection means for at least one memory module, which at least one memory module may or may not be present, and means for transmitting the address signals to the interconnection means if and only if the at least one memory module is present. One embodiment of the present invention includes a line interconnecting the output enable pin of an address buffer to a SIMM socket location which interconnects with a grounded PRES pin on a SIMM when it is installed in the socket. The line to the address buffer enable pin includes a pull-up resistor portion so that the address buffer is disabled unless a SIMM is connected to the socket.
Bibliography:Application Number: DE19916031948T