Integrierte Schaltungsanordnung mit Abschirmungsvorrichtung und Verfahren zu ihrer Herstellung

• Main Authors: ANDERSSON, BO SIXTEN, S-172 47 SUNDBYBERG, SE, LIND, HANS TOMMY, S-117 39 STOCKHOLM, SE
• Format: Patent
• Language: German
• Published: 02.11.1995
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An integrated semiconductor circuit (1) includes a substrate (2), an epitaxial layer (3) having transistor base regions (4), a first (5) and a second (11) insulating oxide layer, and a protective layer (13). The first oxide layer carries heavily doped (n<+>) polycrystalline layers, including an electric contact layer (7), a screening layer (8) and a connecting layer (9). The connecting layer (9) electrically connects the screening layer (8) to the epitaxial layer (3), through the electric contact layer (7). The screening layer prevents the occurrence of inversion (+) and parasite components in the epitaxial layer between the base regions (4). The polycrystalline layer arrangement is simple and can be produced in a common process step. The arrangement is able to withstand high temperatures and enables the second insulating layer (11) to be readily applied.