Referenzmarkierungsstruktur zur Justierung der Ausrichtung von unfertigen Topographien von integrierten Halbleiterschaltungen in Bezug auf aufeinanderfolgende Masken

A reference mark (20) structure for guiding the alignment and true superposition of unfinished topographies of semiconductor integrated circuits (3) to respective masks (21) during the manufacturing process of such circuits, consists of a substantially step-like uneveness produced on the surface of...

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Bibliographic Details
Main Author BURASCHI, MARCO IVANO, I-20091 BRESSO (MILAN), IT
Format Patent
LanguageGerman
Published 05.05.1994
Edition5
Subjects
APPARATUS SPECIALLY ADAPTED THEREFOR
BASIC ELECTRIC ELEMENTS
CINEMATOGRAPHY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:A reference mark (20) structure for guiding the alignment and true superposition of unfinished topographies of semiconductor integrated circuits (3) to respective masks (21) during the manufacturing process of such circuits, consists of a substantially step-like uneveness produced on the surface of a silicon wafer (2) affected by said topography and comprises first (7) and second (10) layers of polycrystalline silicon overlying each other and being covered with a layer (11) of metallic silicide. Advantageously, said layers (7,10,11) are formed over a field oxide surface region (5), and the resulting structure can be readily identified by means of a laser beam optical scanner apparatus (15).
Bibliography:Application Number: DE19896012553T