CMOS Speicher(vom Mehrtorregistertyp) mit leistungsreduziertem Spaltenmultiplexierungsschema

The present invention relates to a multi-port register file memory including a plurality of storage elements in columns. The storage elements are arranged in rows and columns and store data. At least one read port is coupled to each of the storage elements and a sensing device is coupled to the read...

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Bibliographic Details
Main Authors DJAJA, GREGORY, KNEBELSBERGER, DAVID W, SMITH, DOUGLAS D, SLAMOWITZ, MARK
Format Patent
LanguageGerman
Published 28.09.2006
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:The present invention relates to a multi-port register file memory including a plurality of storage elements in columns. The storage elements are arranged in rows and columns and store data. At least one read port is coupled to each of the storage elements and a sensing device is coupled to the read port. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A pair of series transistors coupled together act as the read port while a column mux circuit is coupled to each column and the sensing device. The sensing device includes two inverters comprising input offset and gain stages. An offset device biases the local bitlines at a voltage close to the sense amplifier trip point.
Bibliography:Application Number: DE20016017114T