DE2309616

1409985 Integrated circuits INTERNATIONAL BUSINESS MACHINES CORP 21 Jan 1974 [27 Feb 1973] 02756/74 Heading H1K [Also in Division H3] A data storage circuit (see also Division H3) includes cross-coupled FETs T1, T2 having bipolar transistors T3, T4 as loads. Bipolar transistors T3, T4 formed as late...

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Bibliographic Details
Main Author WIEDMANN, SIEGFRIED KURT. DR., 7000 STUTTGART, DE
Format Patent
LanguageEnglish
Published 11.11.1982
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:1409985 Integrated circuits INTERNATIONAL BUSINESS MACHINES CORP 21 Jan 1974 [27 Feb 1973] 02756/74 Heading H1K [Also in Division H3] A data storage circuit (see also Division H3) includes cross-coupled FETs T1, T2 having bipolar transistors T3, T4 as loads. Bipolar transistors T3, T4 formed as lateral transistors are formed in an N conductive substrate (1, Fig. 3, not shown) while the FETs are formed on elongated P conductive doped regions on the N substrate. N+ doped strips form the source regions of FETs T1, T2. The drain regions are formed by N+ doped areas 6, 7. In the N substrate P doped regions 10, 12 corresponds to the respective collectors of T3, T4 while the P region 11 corresponds to the common emitter region. The interconnections between the various electrodes are made by metallized strips 14, 15.
Bibliography:Application Number: DE19732309616