VERFAHREN ZUR HERSTELLUNG VON INTEGRIERTEN SCHALTUNGEN

• Main Authors: PECORELLA,ALESSANDRO,DR, FUSAROLI,MARZIO,DR
• Format: Patent
• Language: German
• Published: 05.07.1973
• Edition: 1
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An integrated circuit, including several juxtaposed units such as a low-ohmic resistance, an NPN power transistor and a PNP lateral transistor, is produced by forming a corresponding number of N+ strata side by side on a substrate of P-type silicon, epitaxially growing an N-type layer on that substrate to imbed the N+ strata therebetween, isolating the several units from one another by diffusing P-type impurities in intervening regions to divide the N-type layer into sections separated by P-type zones unitary with the substrate, and doping the resulting N-layer sections at selected areas with impurities of either conductivity type through windows formed in an overlying film of silicon oxide. The introduction of P-type impurities is preceded in each case by a more concentrated doping of all or part of the respective area with P+ impurities, followed by a simultaneous diffusion of the P and P+ impurities to a predetermined depth within the respective N-layer sections to form P-type enclaves therein to which metallic terminals are subsequently applied.