Integrated circuit for driving MOS gated power semiconductor devices

• Main Author: WOOD, PETER N., ROLLING HILLS ESTATES, CALIF., US
• Format: Patent
• Language: English; German
• Published: 12.06.1997
• Edition: 6
• Subjects: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS; BASIC ELECTRONIC CIRCUITRY; CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS,e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USERAPPLICATIONS; CONTROL OR REGULATION THEREOF; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER; ELECTRIC HEATING; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERATION; PULSE TECHNIQUE; TECHNICAL SUBJECTS COVERED BY FORMER USPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

In a circuit for driving MOS gated power semiconductor devices (10, 11 Fig 1) connected in a half bridge circuit for supplying an output signal to a load circuit, such as a discharge lamp (60, Figs 5 and 6), a latch circuit 104 is coupled to a timer circuit 101-103 for controlling the frequency at which the MOS gated devices are switched, high and low side dead time delay circuits 107, 108 are each coupled to the latch circuit 104 for delaying an output signal from the latch circuit so as to prevent simultaneous conduction of the MOS gated devices (10, 11), high and low side driver circuits 116, 110 are coupled to the high and low side dead time circuits 107, 108 and provide high and low side outputs for turning on and off the MOS gated devices (10, 11), and dead band control circuit (R IN ,Rf and 21, Fig 3) provides a dead time control signal to the high and low side dead time delay circuits in response to a feedback signal from the load circuit. A further aspect relates to a circuit for driving a load comprising a self oscillating driver circuit and a time delay circuit for preventing simultaneous driving of first and second MOS gated power semiconductor devices. A dimming function is obtained by controlling the feedback voltage by means of a resistor (70, Fig 6).