Low-k dielectric layer patterning method for integrated circuits, involves forming patterned hard mask above low-k dielectric layer of semiconductor metallization layer

The method involves forming a patterned hard mask above a low-k dielectric layer (305) of a semiconductor metallization layer. The low-k dielectric layer is patterned by anisotropically etching using an etch mask. A resist mask is formed above a hard mask layer by patterning hard mask layer to form...

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Bibliographic Details
Main Authors ZISTL, CHRISTIAN, HUEBLER, PETER, LEHR, MATTHIAS
Format Patent
LanguageEnglish
German
Published 02.11.2006
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The method involves forming a patterned hard mask above a low-k dielectric layer (305) of a semiconductor metallization layer. The low-k dielectric layer is patterned by anisotropically etching using an etch mask. A resist mask is formed above a hard mask layer by patterning hard mask layer to form patterned hard mask and resist mask is removed. Unter Verwendung einer nicht-metallischen Hartmaske zum Strukturieren dielektrischer Materialien mit kleinem epsilon moderner Halbleiterbauelemente wird ein höherer Grad an Ätzspurtreue erreicht. Die vorliegende Erfindung kann effizient auf "Kontaktloch zuerst-Graben zuletzt"- bzw. "Graben zuerst-Kontaktloch-zuletzt"-Prozessabläufe angewendet werden.
Bibliography:Application Number: DE20051020060