Process for compensating for etching stress during etching of a semiconductor wafer comprises exposing a substrate bead from the edge of the wafer forming a pattern using photolacquer

Process for compensating for etching stress during etching of a semiconductor wafer comprises exposing a substrate bead from the edge of the wafer forming a pattern using photolacquer. Preferred Features: The bead of silicon is removed from the whole periphery of the wafer. The bead has a width of 1...

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Bibliographic Details
Main Authors TSAI, NIEN-YU, LEE, RAY C, LIN, MING-HUNG, WANG, YUNGING
Format Patent
LanguageEnglish
German
Published 25.04.2002
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Process for compensating for etching stress during etching of a semiconductor wafer comprises exposing a substrate bead from the edge of the wafer forming a pattern using photolacquer. Preferred Features: The bead of silicon is removed from the whole periphery of the wafer. The bead has a width of 1 mm and a depth of 7000-8000 angstroms. The bead is etched in the wafer with the simultaneous formation of deep trenches. Etching is carried out for 10 minutes. Es wird ein Verfahren zum Kompensieren der Ätzbelastung während der Ätzung eines Halbleiterwafers vorgeschlagen. Das Verfahren umfaßt das Entfernen eines Wulstes aus Silizium von dem Rand des Halbleiterwafers während der Ausbildung tiefer Gräben in dem Halbleiterwafer.
Bibliography:Application Number: DE20001050050