Split gate flash memory element arrangement has memory element in p-trough with shallower diffusion depth than n-trough, arranged in n-trough with no electrical contact to substrate

• Main Authors: HABERLA, HOLGER, FREY, MICHAEL
• Format: Patent
• Language: English; German
• Published: 13.09.2001
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

The arrangement has a memory element in a p-trough (1) whose diffusion depth is shallow in comparison to an n-trough (2) and that is arranged in the n-trough so that it has no electrical contact with the substrate (3) at any point. The deep n-trough is arranged in a p-substrate and the n +>-source and drain connections (6,7) are arranged so that they have no electrical contact with the deep n-trough or substrate at any point. Independent claims are also included for the following: a method of clearing a split gate flash memory element arrangement. The arrangement has a memory element in a p-trough (1) whose diffusion depth is shallow in comparison to an n-trough (2) and that is arranged in the n-trough so that it has no electrical contact with the substrate (3) at any point. The deep n-trough is arranged in a p-substrate and the n<+>-source and drain connections (6,7) are arranged so that they have no electrical contact with the deep n-trough or substrate at any point. Independent claims are also included for the following: a method of clearing a split gate flash memory element arrangement. Die Erfindung betrifft die Anordnung eines Split-gate Flash-Speicherelementes und deren Methode zum Löschen in einer speziellen Doppelwannentechnologie in einem Hochvoltprozeß, wodurch die Verwendung positiver Spannungen, wie sie zum Programmieren des Split-gate Flash-Speicherelementes verwendet wird, auch zum Löschen des Elementes eingesetzt werden kann.