Device for generating and controlling dead time of single-photon detector
The utility model discloses a dead time generation and control device for a single photon detector. The dead time generation and control device comprises an avalanche photodiode, a photoelectric converter, an FPGA (Field Programmable Gate Array), a signal start judgment comparator U1: A and a signal...
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Main Authors | , , |
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Format | Patent |
Language | Chinese English |
Published |
07.07.2023
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Subjects | |
Online Access | Get full text |
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Summary: | The utility model discloses a dead time generation and control device for a single photon detector. The dead time generation and control device comprises an avalanche photodiode, a photoelectric converter, an FPGA (Field Programmable Gate Array), a signal start judgment comparator U1: A and a signal peak amplitude judgment comparator U1: B which are connected in sequence, the avalanche photodiode outputs a photoelectric pulse to a photoelectric converter to be converted into an electric signal and then the electric signal is input to the FPGA, and the FPGA inputs the electric signal to the U1: A and the U1: B respectively; the U1: A and the U1: B respectively output clock signals to the FPGA after processing the electric signals; and the FPGA judges whether to collect the electric signal and output the dead time according to the rising edge and the falling edge of the input clock signal. According to the utility model, the comparator U1: A and the comparator U1: B are adopted to generate clock signals, and th |
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Bibliography: | Application Number: CN202223388589U |