System for reducing post pulse and dark count of single photon detection module
The utility model discloses a system for reducing post pulse and dark count of a single photon detection module. The system comprises a laser, a photoelectric converter, an operational amplifier, a clock Fanout chip, a phase-locked loop, a time delay module, the single photon detection module, a com...
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Main Authors | , , |
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Format | Patent |
Language | Chinese English |
Published |
17.01.2023
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Subjects | |
Online Access | Get full text |
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Summary: | The utility model discloses a system for reducing post pulse and dark count of a single photon detection module. The system comprises a laser, a photoelectric converter, an operational amplifier, a clock Fanout chip, a phase-locked loop, a time delay module, the single photon detection module, a comparator and an FPGA control module. The avalanche voltage and the preset voltage value are compared in the comparator, the comparison result is fed back to the FPGA module to adjust the width of the gating signal, and the length of dead time is increased so as to suppress the post pulse. A laser generates an optical signal, the optical signal enters a photoelectric converter to be converted into an electric signal, the electric signal sequentially enters an operational amplifier, a clock Fanout chip, an FPGA control module and a delay module, and then a gating signal is output to a single-photon detection module; the avalanche diode APD generates an avalanche voltage, the avalanche voltage enters the comparator and |
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Bibliography: | Application Number: CN202222656139U |