Array substrate and display panel
The utility model discloses an array substrate and a display panel, and relates to the technical field of display. The array substrate comprises a substrate, a first metal layer, a second metal layer, a common electrode layer and a plurality of connecting patterns. A plurality of scanning lines and...
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Main Authors | , |
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Format | Patent |
Language | Chinese English |
Published |
09.12.2022
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Subjects | |
Online Access | Get full text |
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Summary: | The utility model discloses an array substrate and a display panel, and relates to the technical field of display. The array substrate comprises a substrate, a first metal layer, a second metal layer, a common electrode layer and a plurality of connecting patterns. A plurality of scanning lines and a plurality of gate lines correspondingly connected with the scanning lines are arranged in the first metal layer, and each gate line is connected with one connecting pattern in parallel. The connecting pattern is made of metal materials. The first metal layer is located below the second metal layer, and the second metal layer is located below the common electrode layer. The common electrode layer is provided with a hollow area, and the hollow area is located above the gate line. As the gate lines are connected in parallel with the connection patterns, the resistance of the gate lines after the parallel connection patterns are obtained can be reduced. The hollow area is arranged on the common electrode layer, so th |
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Bibliography: | Application Number: CN202222598796U |