Three-level control system based on ARM and FPGA
The utility model discloses a three-level control system based on an ARM (Advanced RISC Machines) and an FPGA (Field Programmable Gate Array), which comprises the components of the FPGA which is used for generating an interrupt signal; the input end of the sampler is used for being connected with th...
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Main Authors | , , , , , , |
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Format | Patent |
Language | Chinese English |
Published |
28.10.2022
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Subjects | |
Online Access | Get full text |
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Summary: | The utility model discloses a three-level control system based on an ARM (Advanced RISC Machines) and an FPGA (Field Programmable Gate Array), which comprises the components of the FPGA which is used for generating an interrupt signal; the input end of the sampler is used for being connected with the input end and the output end of the three-level circuit and collecting analog signals; the input end of the processor is connected with the sampler and the output end of the FPGA, the output end of the processor is connected with the input end of the FPGA, and the processor is used for controlling the sampler to collect analog signals after receiving the interrupt signals, transmitting the analog signals to the processor for processing to obtain switching time signals of the upper switching tube and the lower switching tube, transmitting the switching time signals to the FPGA for processing, and outputting the switching time signals of the upper switching tube and the lower switching tube. Switching signals of th |
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Bibliography: | Application Number: CN202221750204U |