Comprehensive energy real-time universal simulator internal interface circuit based on multiple FPGAs

• Main Authors: HAN SHENCHAO, WANG JIAGENG, YANG YANCHUN, ZHANG ZHIDA, YU BO, TANG ZHIJIN, WANG HAIWEI, LI MIN, LI ZHENLEI, GUO XIAODAN, PENG CHAODE, MENG ZHAOBIN, SHI FENG, LIU CHANGLI, CAO XIAONAN, LU XIN, ZHU BOLING, WU MINGLEI, CHEN YINQING, ZHANG CHAO, ZHANG JIANHAI
• Format: Patent
• Language: Chinese; English
• Published: 19.01.2021
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The utility model relates to a comprehensive energy real-time universal simulator internal interface circuit based on multiple FPGAs, which is mainly characterized by comprising a high-speed signal receiving unit, a data transmitting unit and a data receiving unit, the high-speed signal receiving and transmitting unit comprises a parallel signal receiving module, a serial signal transmitting module, a serial signal receiving module and a parallel signal transmitting module. The data transmitting unit comprises a serializer, a transmitting channel selector and a data caching unit which are connected in sequence. And the data receiving unit comprises a deserializer, a receiving channel selector and a data cache unit which are connected in sequence. The simulator is reasonable in design, theadvantages of high-speed I/O resources of the FPGA and the technical advantages of hardware parallel computing can be brought into play, the correctness and high efficiency of data communication in the simulator are achieved