Punch-through type medium-low voltage planar TVS chip

• Main Authors: ZHU MING, WANG CHENGSEN, ZHANG CHAO
• Format: Patent
• Language: Chinese; English
• Published: 22.10.2019
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The utility model discloses a punch-through type medium and low voltage planar TVS chip. Wherein the N + diffusion region and the P + diffusion region are arranged on the front surface and the back surface of a P-type silicon wafer; an N-punch-through isolation region is arranged around the P-type silicon wafer, the N + diffusion region and the P + diffusion region, a silicon dioxide passivation layer is arranged at the joint of the inner side of the N-punch-through isolation region and the P + diffusion region, an anode electrode is arranged on the outer surface of the P + diffusion region, and a cathode electrode is arranged on the surface of the N + diffusion region. The preparation method comprises the following steps: 1) oxidizing; 2) photoetching a punch-through ring; 3) phosphorus punch-through diffusion; 4) carving a window on the front surface; the method comprises the following steps of (1) wafer preparation, (2) wafer preparation, (3) wafer preparation, (4) wafer preparation, (5) boron diffusion, (