Wafer level power semiconductor

The utility model discloses a wafer level power semiconductor, including the source region wherein, the active area includes: a conduction type substrate and a conduction type substrate epitaxial layer, form the slot on a conduction type substrate epitaxial layer, electrical conductivity of polycrys...

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Bibliographic Details
Main Authors ZHU YUANZHENG, ZHOU YONGZHEN
Format Patent
LanguageChinese
English
Published 17.04.2018
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The utility model discloses a wafer level power semiconductor, including the source region wherein, the active area includes: a conduction type substrate and a conduction type substrate epitaxial layer, form the slot on a conduction type substrate epitaxial layer, electrical conductivity of polycrystalline silicon packs in the slot, form a conductivity type source electrode on the 2nd conductivitytype tagma, the upper surface of a conductivity type source electrode and a conductivity type substrate epitaxial layer forms the insulating medium layer, form the source electrode pin hole on the insulating medium layer, drain lead hole and grid lead hole, a conductivity type source electrode passes through the source electrode pin hole and is connected with source drain -gate metal level, a conduction type substrate epitaxial layer passes through the drain lead hole and is connected with source drain -gate metal level, and source electrode pin hole, drain lead hole and grid lead hole are same technology step and fo
Bibliography:Application Number: CN201721303825U