Multilayer chip package structure

• Main Author: YE XIUHUI
• Format: Patent
• Language: Chinese; English
• Published: 20.06.2017
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The utility model provides a multilayer chip package structure, includes: a chip circuit layer includes: a first chip, a plurality of weld pads of its upper surface configuration for connect outside wire, a first circuit board lies in this first chip top, and this first circuit board has at least one an online opening and an at least chipset opening, this online opening can make this first circuit board and this first chip combine the back, and the weld pad on this first chip can be come out by this online opening, this chipset opening is arranged in to a first chipset, dispose a plurality of weld pads on this first chipset, expose wherein, be close to this online opening part on this first circuit board and dispose a plurality of weld pads, wherein, be close to this chipset opening part on this first circuit board and dispose a plurality of weld pads. 种多层芯片封装结构，包括：芯片电路层，包括：第芯片，其上表面配置多个焊垫，用于连接外部的导线；第电路板，位于该第芯片上方，该第电路板具有至少联机开口及至少芯片组开口；该联机开口可使得该第电路板及该第芯片结合后，该第芯片上的焊垫可由该联机开口暴露出来；第芯片组，置于该芯片组开口中；该第芯片组上配置有多个焊垫；暴露其中，