Batch test system of chip

• Main Authors: ZHANG BO, LOU FANGCHAO, JIANG XINGYUAN, SHEN JIAHAO, WU ZHONGJIE
• Format: Patent
• Language: Chinese; English
• Published: 19.04.2017
• Subjects: MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; TESTING

The utility model discloses a batch test system of chip, include: main control chip, wait to detect chip, a data bus, the 2nd data bus, main control chip's a bus port, wait to detect the first data port of chip, main control chip's a bus port is through a data bus to waiting that a bus port who detects the chip sends the measuring command information, wait to detect the chip and receive the detection command information that main control chip sent through waiting the first data port that detects the chip, wait to detect the chip and send the response instruction according to the first address information of predetermineeing to main control chip, main control chip judges the operating condition who waits to detect the chip according to the response command information of the first address information of predetermineeing feedback, when the operating condition that waits to detect the chip was unusual, main control chip utilized and waits that it detects the chip to detect unusual the waiting of chip replacement