A multiloop analog quantity synchronous sampling circuit for metering device

• Main Authors: TAN SAI, LI JUN, LUO QIN, HAN TAO
• Format: Patent
• Language: Chinese; English
• Published: 27.07.2016
• Subjects: BASIC ELECTRONIC CIRCUITRY; CALCULATING; CODE CONVERSION IN GENERAL; CODING; COMPUTING; COUNTING; DECODING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS

The utility model provides a multiloop analog quantity synchronous sampling circuit for metering device, including AD conversion chip, controller and FPGA, the CONV signal end of AD conversion chip, CS signal end, BUSY signal end link to each other with FPGA's IO port, DATA signal end links to each other with the DATA signal end of controller, and CLK signal end links to each other with the CLK signal end of controller, FPGA's IO pin, the INT signal end of controller links to each other with FPGA's IO pin. The utility model discloses owing to adopted the controller that has the DMA passageway to increased FPGA and carry out the control of data sampling and transmission between controller and AD conversion chip, therefore do not needed the core operating program of controller and other hardware resource to participate in in data sampling and transmission course, reduced the resource cost of controller, makeed the controller operation more reliable and more stable, the sampling rate is higher, and the real -tim