IIC bus experiment device carrying out adjusting through serial port
The utility model relates to a bus experiment device. To overcome the defects in the prior art, data of a certain register externally arranged can be checked or corrected visually through a command editing window of an upper computer, and an obtained return value can be displayed at the PC end visua...
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Main Authors | , , , , , |
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Format | Patent |
Language | English |
Published |
15.04.2015
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Subjects | |
Online Access | Get full text |
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Summary: | The utility model relates to a bus experiment device. To overcome the defects in the prior art, data of a certain register externally arranged can be checked or corrected visually through a command editing window of an upper computer, and an obtained return value can be displayed at the PC end visually. An operator can utilize an IIC protocol more conveniently and clearly to adjust and test a chip. According to the technical scheme, an IIC bus experiment device carrying out adjusting through a serial port comprises an upper computer UART interface controller, a protocol converting unit, an IIC bus interface controller and a clock managing unit. The clock managing unit is connected with the upper computer UART interface controller, the protocol converting unit and the IIC bus interface controller. The upper computer UART interface controller receives and transmits the data through the serial port, and the IIC bus interface controller receives and transmits the data of the designated register externally arranged through an IIC bus. The bus experiment device is mainly applied to bus experiments. |
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Bibliography: | Application Number: CN20142751669U |