Device for configuring a plurality of field programmable gate arrays (FPGA) by utilizing clock drivers

The utility model provides a device for configuring a plurality of field programmable gate arrays (FPGA) by utilizing clock drivers, comprising a configuration chip programmable read-only memory (PROM), the clock drivers and an FPGA chip, wherein a clock (CLK) single wire and a DATA signal wire of t...

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Bibliographic Details
Main Authors WANG YING, LIU XINCHUN, ZHENG CHENMING, YANG XIAOJUN, HAO ZHIBIN, LIU SHENGJIE, LIANG FAQING, YAO WENHAO, WANG HUI, SHAO ZONGYOU
Format Patent
LanguageChinese
English
Published 07.03.2012
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The utility model provides a device for configuring a plurality of field programmable gate arrays (FPGA) by utilizing clock drivers, comprising a configuration chip programmable read-only memory (PROM), the clock drivers and an FPGA chip, wherein a clock (CLK) single wire and a DATA signal wire of the configuration chip programmable read-only memory are respectively connected with the clock drivers, the output end of the clock driver, connected with the CLK signal wire, is connected with a clock input end of the clock driver of the FPGA chip, and the output end of the clock driver, connected with the DATA signal wire, is connected with a data input end of the FPGA chip. In the utility model, a great amount of FPGAs can share the same PROM, the cost during configuration can be effectively reduced and the configuration flexibility can be improved.
Bibliography:Application Number: CN20112259179U