Gate structure, semiconductor memory device having the gate structure and methods of fabricating the same

• Main Author: SEOL KWANG-SOO,KIM BYUNG-KI,LEE EUN-KYUNG,MIN YO-SEP,CHO KYUNG-SANG,LEE JAE-HO,CHOI JAE-YOUNG
• Format: Patent
• Language: English
• Published: 16.05.2007
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A gate structure using nanodots as a trap site, a semiconductor device having the gate structure and methods of fabricating the same are provided. The gate structure may include a tunneling layer, a plurality of nanodots on the tunneling layer, and a control insulating layer including a high-k dielectric layer on the tunneling layer and the nanodots. A semiconductor memory device may further include a semiconductor substrate, the gate structure according to example embodiments on the semiconductor substrate and a first impurity region and a second impurity region in the semiconductor substrate, wherein the gate structure is in contact with the first and second impurity regions.