CMOS silicide metal gate integration

The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal...

Full description

Saved in:
Bibliographic Details
Main Authors KEDZIERSKI JAKUB T, KU VICTOR, STEEGEN AN L, MOCUTA ANDA C, CABRAL CYRIL JR, NARAYANAN VIJAY, BOYD DIANE C, LI YING, SURENDRA MAHESWAREN, LEE WOO-HYEONG, KAPLAN RICHARD D, AMOS RICKY S
Format Patent
LanguageChinese
English
Published 29.09.2010
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
Bibliography:Application Number: CN200580002708