Encapsulated chip scale package having flip-chip on lead frame structure and method

In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP o...

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Bibliographic Details
Main Author FAUTY JOSEPH K.,LETTERMAN JAMES P. JR.,THIENPONT DENISE
Format Patent
LanguageEnglish
Published 21.02.2007
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.
Bibliography:Application Number: CN200610115603