Semiconductor memory device

A semiconductor memory device wherein, in order to control the current consumed in a column address counter and latch block in a read operation, delay units disposed in the column address counter and latch block perform a shifting operation according to a signal CASP6, which is enabled in the write...

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Bibliographic Details
Main Author SHIN BEOM-J
Format Patent
LanguageChinese
English
Published 15.06.2011
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A semiconductor memory device wherein, in order to control the current consumed in a column address counter and latch block in a read operation, delay units disposed in the column address counter and latch block perform a shifting operation according to a signal CASP6, which is enabled in the write and read operations, and a signal WT6RD5Z, which is enabled in the write operation and disabled in the read operation. Accordingly, unnecessary current consumed in the read operation can be reduced.
Bibliography:Application Number: CN20051120242