Multilayered chip capacitor

A multilayered chip capacitor including a capacitor main body including a plurality of dielectric layers, which are laminated; at least one pair of first and second internal electrodes, each of which is formed on the corresponding one of the plural dielectric layers and includes at least one lead ex...

Full description

Saved in:
Bibliographic Details
Main Author LEE BYOUNG HWA,PARK DONG SEOK,SHIM CHANG HOON,PARK SANG SOO,PARK MIN CHEOL
Format Patent
LanguageEnglish
Published 15.03.2006
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:A multilayered chip capacitor including a capacitor main body including a plurality of dielectric layers, which are laminated; at least one pair of first and second internal electrodes, each of which is formed on the corresponding one of the plural dielectric layers and includes at least one lead extended to one end of the corresponding dielectric layer; a plurality of external terminals formed on the outer surface of the capacitor main body, and respectively connected to the first and second internal electrodes through the leads; and at least one opened region, formed through the inner area of each of the first and second internal electrodes, for branching the flow of current so as to increase the offset quantity of parasitic inductances between the first and second internal electrodes.
Bibliography:Application Number: CN200510001614