Low latency time memorizer system access

• Main Author: BLUMRICH MATTHIAS A.,CHEN DONG,CHIU GEORGE L.,CIPOLLA THOMAS M.,COTEUS PAUL W.,GARA ALAN G.,GIAMPAPA MARK E.,HEIDELBERGER PHILIP,KOPSCAY GERALD V.,MOK LAWRENCE S.,TAKKEN TODD E
• Format: Patent
• Language: English
• Published: 18.01.2006
• Subjects: CALCULATING; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS; PHYSICS; PRINTED CIRCUITS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.