Clock decimal frequency dividing method

The invention discloses a decimal frequency division method for clock. According to m frequency division and m+1 frequency division inserting method to take decimal frequency division to the clock to gain a basic clock and generate an enable signal. Using the enable signal reforming the basic clock...

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Bibliographic Details
Main Author GUOJIE PAN
Format Patent
LanguageEnglish
Published 20.07.2005
Edition7
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
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Summary:The invention discloses a decimal frequency division method for clock. According to m frequency division and m+1 frequency division inserting method to take decimal frequency division to the clock to gain a basic clock and generate an enable signal. Using the enable signal reforming the basic clock to gain the needed frequency clock signal. The invention can improve the equitability of the clock, and by deducting or increasing impulse it also can improve duty ratio and the capability of clock. Thus, the decimal frequency division clock gained from the invention is almost the same as double frequency first then decimal frequency division on capability and quality.
Bibliography:Application Number: CN2004102149