Clock decimal frequency dividing method
The invention discloses a decimal frequency division method for clock. According to m frequency division and m+1 frequency division inserting method to take decimal frequency division to the clock to gain a basic clock and generate an enable signal. Using the enable signal reforming the basic clock...
Saved in:
Main Author | |
---|---|
Format | Patent |
Language | English |
Published |
20.07.2005
|
Edition | 7 |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | The invention discloses a decimal frequency division method for clock. According to m frequency division and m+1 frequency division inserting method to take decimal frequency division to the clock to gain a basic clock and generate an enable signal. Using the enable signal reforming the basic clock to gain the needed frequency clock signal. The invention can improve the equitability of the clock, and by deducting or increasing impulse it also can improve duty ratio and the capability of clock. Thus, the decimal frequency division clock gained from the invention is almost the same as double frequency first then decimal frequency division on capability and quality. |
---|---|
Bibliography: | Application Number: CN2004102149 |