Method for multilevel copper interconnects for ultra large scale integration

• Main Authors: J.E. GEUSIC, K.Y. AHN
• Format: Patent
• Language: Chinese; English
• Published: 22.09.2004
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; CHEMICAL SURFACE TREATMENT; CHEMISTRY; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING MATERIAL WITH METALLIC MATERIAL; COATING METALLIC MATERIAL; DIFFUSION TREATMENT OF METALLIC MATERIAL; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL; METALLURGY; SEMICONDUCTOR DEVICES; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION

一种制造集成电路的方法，该方法利用金属氧化物薄膜(220)作为籽晶层以在集成电路中建立多层互连结构。在晶片(210)上淀积金属氧化物薄膜(220)，按与金属线图形(215)对应的图形利用标准光刻以暴露金属氧化物膜(220)。该金属氧化物膜(220)转化为金属层(240)，然后通过选择性CVD或者化学镀可在转化的氧化膜(260)上淀积金属膜(250)。然后以利用通孔光刻的类似工艺制造通孔(280)。继续该工艺直到制造出期望的多层结构。 A method of manufacturing integrated circuits using a thin metal oxide film as a seed layer for building multilevel interconnects structures in integrated circuits. Thin layer metal oxide films are deposited on a wafer, and standard optical lithography is used to expose the metal oxide film in a pattern corresponding to a metal line pattern. The metal oxide film is converted to a layer of metal, and a metal film may then be deposited on the converted oxide film by either selective CVD or electroless plating. Via holes are then fabricated in a similar process using via hole lithography. The process is continued until the desired multilevel structure is fabricated.